An Analytical Placer for VLSI Standard cell placeme

1208IEEETRANSACTIONSONCOMPUTER-AIDEDDESIGNOFINTEGRATEDCIRCUITSANDSYSTEMS,VOL.31,NO.8,AUGUST2012AnAnalyticalPlacerforVLSIStandardCellPlacementJianliChenandWenxingZhuAbstract—Placementistheprrucialstepinverylargescaleintegration(VLSI)physicaldesign,becauseitaffectsroutability,performance,paper,wedevelocerconsistsoftwophases,multilevelglobalplacement(GP)anddetailedcellplacement(DP).InthestageofGP,duringtheclusteringstage,weuseanonlinearprogrammingtechniqueandabest-choiceclusteringalgorithmtotakeaglobalviewofthewholenetlistandplacementinformation,andthenuseaniterativelocalrefinementtechniqueduringthedectageofDP,wedevelopafastlegalizationalgorithmtomakethesolutionbyglobalpposedalgomentalresultsshowerms—Analyticalapproach,detailedplacement,globalplacement,standardcellplacement,verylargescaleintegration(VLSI)uctionTHEVERYlargescaleintegration(VLSI)cellplacementprobleminvolvesplacingasetofcellsonadesignregionforagivennetlist[1].Thenetlistspecifiesinterconnectionsbetweenthyoutinformationincludesthewidthandheightofeachcell,andthelocationsofI/lofcellplacementistodeterminethelocationofeachcellsuchthatnocelloverlapswiththeother,Icellplacementproblemisnondeterministicpolynomial(NP)-complete,sinceinthesimplestcase,theproblemof1-Dplacementofthecircu,theoptimallineararrangementproblem,isNP-complete[2].Hence,itManuscriptreceivedMay24,2011;revisedAugust7,2011,October3,2011,andJanuary23,2012;acceptedFebruary27,currentversionJuly18,rkwassupportedinpartbytheNationalScienceFoundationofChina,underGrants61170308and10931003,inpartbytheNationalKeyBasicResearchSpecialFoundationofChina,underGrant2011CB808000,andinpartbytheResearchFundfortheDoctoralProgramofChina,horsarewiththeCenterforDiscreteMathematicsandTheoret-icalComputerScience,FuzhouUniversity,Fuzhou350108,China(e-mail:wxzhu@).ColorversionsofoneormoreofthefiguresinthispaperareavailableonlineatlObjectIdentifier10.1109/TCAD.2012.2190289isachallengetodesignefficientplacementalgorithmsforproducinghighqualityplacementsolutionsofcircuitswithmillionsofcells[3].Totalwirelengthisthemostcommonlyusedobjectiveinplacementformulations[3].Thisisbecausemi,withlesswirelengthandroutingdemand,,theperformanceofcircuitscanbebetterwithsho,powerconsumptioncanbeformulatedasawirelengthproblem,twidelyusedestimationisthehalf-perimeterwirelength(HPWL)[4].TheHPWLofanetisthehalfoftheperipaper,edifferentdesignsmayrequiredifferentcellsanddifferentdesignstylesmayintroducedifferentconstraints,ell,standardcell,gatearray,ledcomparisonofthefourdesignstylescanbefoundin[3].Sincethestandardcellplacementtakesshorttimetoimplement,itispopularforapplication-specificintegratedcircuitdesigns,andardcelldesign,allcellshavethesameheight,andtheplacementofcellshastobealignedwithsomeprespecifipaper,lacementisacrucialstepinVLSIphysicaldesign,lacementalgorithmscanbeclassifiedintothreemajortypes:metaheuristicmethods,min-cut,uristicmethodsforplacementincludethesimulatedannealingalgorithm,thegeneticalgorithm,ulatedannealing-basedplacers[6]–[8]r,itishardlyextendedtoapplyonlargescalecircuits[5].Manymetaheuristicalgorithms,suchasthegeneticalgorithm,arealsousedtosolvethisproblem[9]–[12].Theauthorsin[12]presentedormswellc2012IEEE0278-0070/$31.00