Architecture and hardware for scheduling gigabit packet streams

iiiiiiiiii*Architecture and Hardware for Scheduling Gigabit Packet Streams

iiii{rk, sudha, schwan}@ {richwest@}

Center for Experimental Research in Computer Systems *Department of Computer Science

Georgia Institute of Technology Atlanta, GA 30332-0280 Boston University Boston, MA

iiiii

Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan and Richard West*

i

Abstract

We present an architectre and hardware for

scheduling gigabit packet streams in server clusters that

combines a Network Processor datapath and an FPGA

for uuse in server NICs and suerver cluster switches. Our

uarchitectural framework can provide EDF, static-priority,

fair-share and DWCS native scheduling support for best-effort and real-time streams. This allows – (i)

interoperability of schedling hardware spporting

different scheduling disciplines and (ii) helps in

providing customized scheduling solutions in server

clusters based on traffic type, stream content, stream

uvolme and clster hardware sing a hardware

implementation of a scheduler running at wire-speeds.

The architecture scales easily from 4 to 32 streams on a

single Xilinx Virtex 1000 chip and can support 64-byte -

1500-byte Ethernet frames on a 1 Gbps link and 1500-byte Ethernet frames on a 10 Gbps link. A running

hardware prototype of a stream scheduler in a Virtex

1000 PCI card can divide bandwidth based on user

specifications and meet the temporal bounds and packet-time requirements of multi-gigabit links.

1.0 Introduction