Effects of Wafer Bow and Warpage on Performance of Electrostatic Ch

Effects of Wafer Bow and Warpage on Performance of

Electrostatic Chucks in High Volume Manufacturing

Piotr Kurkowski, Sergei Drizlikh, Roger Sarver, Heath Angis, Patrick Loisel

National Semiconductor Corporation, 5 Foden Road, South Portland, Maine, 04106 USA

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Abstract

This paper presents learnings authors gained when dealing

with back side pressure faults (BSPF) on 200mm

interconnect deposition tools equipped with minimum

BSPF occurs whenever a set point pressure is not reached

due to backside argon leakage on wafer sides; halting

further processing in the chamber in case of a wafer

contact area (MCA) electrostatic chucks (ESC). It was

found that BSPF’s occurred more likely on chucks running

mostly BiCMOS product. BiCMOS product was four times

more susceptible to experience this fault than CMOS due to

higher wafer bow and warpage which were traced to

recrystallization of backside polysilicon at RTP emitter

anneal. Moreover, a cost-effective rework scheme was

implemented to prolong the life of ESC’s. Long term

solution of reducing wafer bow and warpage process is

also being pursued.

Keywords

Electrostatic chuck (ESC), wafer warpage, wafer bow,

BiCMOS

INTRODUCTION

In the course of semiconductor process flow silicon wafers

develop bow and warpage due to different intrinsic

properties of films added or removed to both front and back

sides. However, there are process steps that require nearly

perfect wafer planarity such as extreme UV

photolithography for depth of focus control and deposition

and etch tools that require wafer temperature control.

The purpose of an ESC in metal deposition process is to

clamp (chuck) down wafers against a back side gas flow

which is used for temperature control.

Chucking is achieved using a bipolar ESC which resembles

a parallel plate capacitor with one of the plates being the

wafer (see Figure 1 and 2). Wafer is first electrostatically

flattened and then backside argon is flown at a controlled

rate and a desired pressure is expected to build up within a

set time.

Figure 1. Actual MCA ESC surface

made by Applied Materials Inc.

<>BACKbreakage.

Figure 2. Schematic illustration of a bipolar ESC.

PROBLEM DESCRIPTION & INVESTIGATION

While working on reducing the number BSPF occurrences

we observed that the frequency of a BSPF was four times

higher on BiCMOS than CMOS technology flow.

Analyzing the BSPF distribution between metal deposition

tools, we discovered that the ESC age and usage are

significant factors in BSPF occurrence frequency.

However, one question remained: what is different about

the two types of product wafers? It was suspected that

wafer geometry might be a significant factor. Using

ADE’s 9500 UltraGage metrology tool we measured shape

and flatness of wafers at metal deposition step. Table 1

reveals that there is a significant difference in planarity

between CMOS and BiCMOS types. Wafers on BiCMOS

process flow had much higher bow (more convex) and

warpage.

Table 1. BiCMOS has significantly higher non-planarity compared to CMOS product wafers.

Bow (µm) Warpage (µm)

CMOS 20 45

BiCMOS 46 112

To identify which process step is responsible for inducing

excessive wafer bow/warpage on BiCMOS flow, we

measured these parameters at various key process steps.

1

Figure 3. BiCMOS warpage as measured at various

process steps.

The emitter anneal step is the responsible step (see Figure

3). Since the wafer at this step has amorphous silicon on

the back side and the anneal is over 900 deg C we suspect

that the recrystallization of the silicon is the root cause for

excessive bow/warpage [1].

Furthermore, our investigation revealed that BSPF are

confined to certain ESC’s. Following vendor

recommendation, we used upside down wafer particle scan

to diagnose how well a test wafer is pulled flat against the

ESC surface. The map generated from frequently aborting

ESC was compared against a healthy ESC. As can be seen

in Figure 4, the aborting ESC has missing rings of contact

pads while the healthy ESC has full pad pattern.

Figure 4. Left, worn ESC MCA pads with frequent

BSPF’s. Right, healthy ESC with no BSPF’s.

CONTAINMENT

The initial containment involved trying to With upside

down test serving as a visual indicator of chucking strength

along with the associated frequency of faults, worst e-chucks were identified. The next step was to use in-house

automation systems to route BiCMOS WIP to chambers

not suffering from BSPF’s. Lastly, authors implemented a

cost-effective method to rework worn ESC’s thus offsetting

the need to purchase new ones. At 1/5th the cost of a new

chuck this amounts to significant savings.

The actual rework procedure consists of stripping the old

MCA pads and redepositing new ones provided that the

ESC does not suffer from other defects. Moreover, the

2<>BACKrefurbished ESC’s had their pad count doubled to decrease

the rate of wear. These measures immediately decreased

the frequency of the pressure faults (see Figure 5), which in

turn, reduced product scrap, tool down time and the need

for engineering intervention.

Figure 5. Normalized Pareto plot of tool recovery faults

during three consecutive periods.

BACKSIDE FILM INVESTIGATION

With initial investigation pointing toward the increase in

the crystalline order of the backside film(s) during emitter

anneal as the most significant source of wafer warpage on

BiCMOS process flow, we measured warp trend for

different backside films. We found that the furnace

deposition of amorphous polysilicon, which inevitably

occurs on both sides of a wafer, and its subsequent RTP

anneal induce the greatest amount warpage as seen in

Figure 6. Since low warpage is highly desirable, a new

backside polysilicon strip would have to be added to the

existing process flow, however, moving an earlier backside

strip to post polysilicon deposition is more efficient in this

case. Efforts are currently underway to qualify and

implement this change in the BiCMOS process flow.

Figure 6. Warp trend by process operation for

different backside films.

CONCLUSIONS

National's 200mm fab is a high volume factory with a

variety of process technologies. Wear of ESC’s is expected,

however, higher than normal amount was observed on

ESC’s running predominantly BiCMOS wafers. These

ESC’s have a distinctive wear pattern and experience

significantly more BSPF’s on BiCMOS wafers which have

much higher bow and warpage. This non-planarity was

traced to RTP anneal step of backside polysilicon film

where our current effort is directed. Faced with demands

of manufacturing the authors were able to contain the issue

through automated WIP routing and provided a cost-effective method to restore ESC’s to a newer condition.

ACKNOWLEDGMENTS

We would like to thank Jeff Jernigan, section head of Thin

Films group, for making the writing of this paper possible.

REFERENCES

[1] Campbell, S.A., The Science and Engineering of

Microelectronic Fabrication, 2nd ed., Oxford University

Press, New York, NY (2001).

3<>BACKAUTHOR BIOGRAPHY

Piotr Kurkowski has been with National Semiconductor

since 2001 in Thin Films group as a CVD/PVD

metallization process engineer.

Sergei Drizlikh has been with National Semiconductor

since 2001 in Unit Process Development group as a

CVD/PVD metallization process development engineer.

Roger Sarver has been with National Semiconductor since

1996 in Thin Films group as a CVD/PVD metallization and

RTP equipment engineer.

Heath Angis has been with National Semiconductor since

1999 in Thin Films group as a CVD/PVD metallization

equipment engineer.

Patrick Loisel has been with National Semiconductor

since 1997 in Process Development/Integration group as a

process integration technician.