Datasheet_RTL8671B_v04_preliminary

RTL8671B/ RTL8671BH

Integrated ADSL2+ Router Controller

Datasheet

Rev. 0.4

6 May, 2008

Track ID: xxxx-nnnn-nn

Integrated ADSL2+ Router Controller i Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

COPYRIGHT

©2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be

reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any

language in any form or by any means without the written permission of Realtek Semiconductor

Corp.

DISCLAIMER

Realtek provides this document “as is”, without warranty of any kind, neither expressed nor

implied, including, but not limited to, the particular purpose. Realtek may make improvements

and/or changes in this document or in the product described in this document at any time. This

document could include technical inaccuracies or typographical errors.

TRADEMARKS

Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this

document are trademarks/registered trademarks of their respective owners.

CONFIDENTIALITY

This document is confidential and should not be provided to a third-party without the permission

of Realtek Semiconductor Corporation.

USING THIS DOCUMENT

This document is intended for the software engineer’s reference and provides detailed

programming information.

Though every effort has been made to ensure that this document is current and accurate, more

information may have become available subsequent to the production of this guide. In that event,

please contact your Realtek representative for additional information that may help in the

development process.

REVISION HISTORY

Revision

0.0

0.1

0.2

0.3

0.4

Release Date

2008/01/18

2008/01/23

2008/01/30

2008/01/31

2008/05/06

Summary

First release.

n Correcting pin 113 as ‘OVDD’

n Block diagram added

n Correcting pin 12 as ‘VSS’

n Correcting polarity of ‘U1ID’

n ‘U1ID’ should be input only, not I/O

n RTL8671BH added

Integrated ADSL2+ Router Controller ii Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

Table of Contents

2.

2

3.

2

4.

3

5.

.4

6.

5

7.

10

8.

11

8.1.

DC

11

8.1.1.

Absolute 11

8.1.2.

Recommended 11

8.1.3.

11

8.1.4.

12

8.1.5.

ADSL Interface .12

8.2.

AC

.12

8.2.1.

FLASH – 12

8.2.2.

FLASH – .13

8.2.3.

13

8.2.3.1

SDRAM 13

8.2.3.2

SDRAM 14

8.2.3.3

SDRAM Access .15

8.2.4.

16

8.2.4.1

16

8.2.4.2

16

8.2.4.3

.16

8.2.5.

16

8.2.6.

18

8.2.7.

18

8.2.8.

19

9.

20

10.

22

11.

Integrated ADSL2+ Router Controller iii Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

List of Tables

TABLE

1

TABLE

2

TABLE

3

TABLE

4

TABLE

5

TABLE

6

TABLE

7

TABLE

8

TABLE

9

TABLE

10

TABLE

11

TABLE

12

TABLE

13

TABLE

14

TABLE

15

TABLE

16

TABLE

17

PIN

DESCRIPTIONS OF

RTL8671B/

RTL8671BH

(128-PIN

LQFP)....................................................................5

ABSOLUTE

MAXIMUM

11

RECOMMENDED

OPERATION

11

POWER

11

REFERENCE

12

ADSL

INTERFACE

CLOCK

12

PARALLEL

FLASH

12

SDRAM

INPUT

13

SDRAM

OUTPUT

14

SDRAM

ACCESS

CONTROL

15

AFE

MASTER

16

AFE

TX

16

AFE

RX

16

JTAG

INTERFACE

16

RESET

18

VREF

18

DIMENSION OF

21

List of Figures

FIGURE

1

FIGURE

2

FIGURE

3

FIGURE

4

FIGURE

5

FIGURE

6

FIGURE

7

FIGURE

8

FIGURE

9

FIGURE

10

FIGURE

11

FIGURE

12

APPLICATION

DIAGRAM

I...................................................................................................................................2APPLICATION

DIAGRAM

II..................................................................................................................................2BLOCK

3PIN-OUT

4FLASH

ACCESS

13SDRAM

INPUT

14SDRAM

OUTPUT

.14SDRAM

ACCESS

CONTROL

15BOUNDARY-SCAN

GENERAL

17BOUNDARY-SCAN

RESET

17RESET

18DRAWING OF

20

Integrated ADSL2+ Router Controller iv Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

1. General Description

The Realtek

RTL8671B/ RTL8671BH are integrated SoC featuring a RISC, an ADSL2+ Discrete

Multi-tone (DMT) data-pump, a hardware-based ATM Segmentation and Reassembly (SAR),

two 10/100Mbps IEEE 802.3 compliant MACs with an embedded Ethernet transceiver, and a

USB PHY port. Mated with the Realtek

RTL8271B (ADSL2+ Analog Front End),

RTL8671B/

RTL8671BH provide a low cost integrated solution for ADSL2+ CPE modems, routers, or

gateways.

RTL8671B/ RTL8671BH encompass high-performance DSP technologies, optimized mix-signal

designs, and an efficient architecture to provide a seamless WAN to LAN router controller. The

embedded RISC network processor supports the MIPS I instruction set along with DSP

extensions and achieves a 340MHz clock rate in a six-stage pipeline to support layer 2, 3, and

other upper layer applications.

The DMT engine supports the upstream data rate from 32kbp to above 3Mbps and the

downstream data rate from 32kbps to above 24Mbps throughput, and complies with:

n ANSI T1.413 Issue 2

n ITU-T G.992.1 (G..dmt) Annexes A and B

n G.992.2 (G..lite) Annexes A and B

n G.992.3 ADSL2 () Annexes A, B, I, J, L, and M

n G.992.4 ADSL2 ()

n G.992.5 ADSL2+

The Ethernet interface offers high-speed transmission over CAT-5 UTP cable or CAT-3 UTP

(10Mbps only) cable. Ethernet functions such as Crossover Detection & Auto-Correction and

polarity correction are implemented to provide robust transmission and reception capability at

high speeds.

Integrated ADSL2+ Router Controller 1 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

2. Features

n Two-chip ADSL2+ CPE solution:

RTL8671B/ RTL8671BH (ADSL2+/Network

Processor SoC) +

RTL8271B (ADSL2+

Analog Front End).

n Field proven DMT data-pump complies

with ANSI T1.413 Issue 2, ITU-T G992.1,

G.992.2 , G.992.3, G.992.4, G.992.5

supporting Annexes A, B, I, J, L, and M.

Supports S=1/3 coding.

n High performance embedded RISC with

MMU, TLB and DSP instruction extension.

n Embedded hardware-based ATM SAR: up

to 8 distinct VCs—ATM AAL5 adaptation,

F4/F5 OAM cell, HEC, CRC, IP/TCP/UDP

checksum offloading, and error packet

filtering— and QoS supported for CBR,

UBR, rt-VBR, and nrt-VBR.

n Embedded 10/100 Base-TX Ethernet MAC

and transceiver supporting Crossover

Detection & Auto-Correction and polarity

correction, IP/TCP/UDP checksum offload

supported as well.

n One on-chip USB PHY port supporting the

host/device mode

n Support serial SPI interface for device

control

n Network device management via HTTP,

SNMP, and CLI (UART).

n IP layer processing, DHCP, NAT, and

typical higher layer applications supported

n 16-bit-wide, 166MHz SDRAM support up

to 256Mb

n 8/16-bit-wide parallel/SPI Flash support up

to 128Mb

n 3.3V signaling, 1.2V core voltage; a

embedded linear regulator controller to

reduce an external LDO

n Two 32-bit timers and a watchdog timer

n Embedded “Dying-Gasp” detection circuit

n EJTAG interface

n Package of 128-pin LQFP available

Integrated ADSL2+ Router Controller 2 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

3. System Applications

USB-BRJ45RJ11AFERTL8271BButtons& LEDsRS-232RTL8671BLQFP-128SDRAM

FLASHParallel/SPIFigure 1 Application Diagram I

RJ45SDRAM16M/32MB(x16)FLASHParallel/SPI

RJ11AFERTL8271BAntennaAntennaUSB-WIFI, 11b/gRTL8187SURS-232Buttons& LEDsRTL8671BHLQFP-128Figure 2 Application Diagram II

Integrated ADSL2+ Router Controller 2 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

4. Block Diagram

UARTGPIOEJTAGCPUMemoryController16-bitNOR, SPIFLASH ControlI-CACHED-CACHEI-RAMD-RAMSPIArbiterInterruptControlATMSARUSBOTGw/ PHYSDRAMControlOBCClock &System control

DMT &AFE I/FENETPHY(w/ MAC),LEDFigure 3 Block Diagram

Integrated ADSL2+ Router Controller 3 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

5. Pin Assignments

MD14MD15WE#OVDDRAS#CAS#MCS3#DGNDMCS2#IVDDMA0MA1MA2MA3OVDDMA4MA5MA6MA7IVDDMA8MA9MA10MA11MA12OVDDMA13MA14MA15MA16MA17MA297372717MD13MD12IVDDMD11MD10OVDDMD9MD8MD7MD6SDCLKMD5IVDDMD4DGNDMD3OVDDENUSBOTGMD2MD1MD0CK25MOUTCKSELVDD12XIXOVSSNCVDD33IBREFVSSVREF9798995976453RTL8671BLQFP-42414433MA19/SFCK/SVCKMCS0#MA20MA21/NICLED0OVDDMA22/NICLED1DGNDNICLED2IVDDNICLED3USBLED1RSRVD(NC)GPB7/JTDOGPB6/JTMSGPB5/JTDIGPB4/JTRST#GPB3/JTCKGPB2/URTS#/SVDOGPB1/UTXD/SVDIGPB0/URXD/SVCS#IVDDGPA7/UCTS#/SVCKGPA6PWRRST#AFPWDNOVDDTESTMODEAFCTRLIVDDAFCLWD/SF_DIAFRXD3AFRXD2829303132

Figure 4 Pin-out Diagram

Integrated ADSL2+ Router Controller

VCTLVDD33VDD12TXOPTXONVSSRXIPRXINVDD12VDD12CKINVSSVDD12VDD33RSRVD(NC)RSRVD(NC)VSSVSSU1DMU1DPU1IDU1VBUSVDD33DGNDGPA5/SVCS#IVDDAFTXD0AFTXD1AFTXD2AFTXD3AFRXD0AFRXD14 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

6. Pin Descriptions

Table 1

Symbol

Pin Descriptions of RTL8671B/ RTL8671BH (128-pin LQFP)

Type

100/10 Physical Layer

RXIP

RXIN

TXOP

TXON

IBREF

7

8

4

5

126

I

O

I

Ethernet physical layer differential

RX pins

Ethernet physical layer differential

TX pins

Pull-down externally with 2.5k Ohm

for PHY reference

Ethernet PHY LED

NICLED[3:0] 55, 57, 59, 61 O LED driving signals for the

embedded Ethernet PHY;

Pins MA[22:21] sharing with

NICLED[1:0]

Clock & Reset

XI

XO

CKSEL

121

122

119

I

O

I

25MHz crystal clock input.

25MHz crystal clock output.

Reference clock selection; tied to

1.2 to select XO (25MHz), VSS to

select CKIN (35.328MHz)

PWRRST# 41 I

SPI Control Interface

SVCS# 45 O SPI chip select pin (shared with

GPB0 and URXD)

SVDI 46 I SPI data in (shared with GPB1 and

UTXD)

SVDO 47 O SPI data out (shared with GPB2

and URTS#)

SVCK 48 O SPI reference clock (shared with

GPA7 and UCTS#)

USB Interface

System reset.

Description 128 Pin#

Integrated ADSL2+ Router Controller 5 Track ID: xxxx-nnnn-nn Rev. 0.4

U1DP, U1DM

20, 19 I/O

RTL8671B/ RTL8671BH

Datasheet

Differential data I/O of USB PHY 1

To

RTL8671BH: either host/device

mode supported; configured by

U1ID

To

RTL8671B: device mode

supported only

U1ID (NC) 21 I To

RTL8671BH: Pull-low/high to

select PHY 1 as host/device

To

RTL8671B: NC

U1VBUS 22 I USB VBUS detect pin; used for

PHY 1 configured in device mode

USBLED1

ENUSBOTG

54

114

AFE Interface

AFPWDN

AFRXD[3:0]

AFTXD[3:0]

40

34, 33, 32, 31

30, 29, 28, 27

O

I

O

Power down control to AFE

Data input from AFE

Data output to AFE

Pins AFTXD[3:2] strap into register

values as OCCLK_SEL[1:0], which

defines the CPU speed. For

RTL8671B/ RTL8671BH, the

O

O

USB LED driver output

Enable USB OTG block

AFTXD[3:2] should be strictly

pulled as ‘10’.

AFCLWD

CKIN

AFCTRL

VREF

35

11

37

128

Memory Bus

MD[15:0] 95, 96, 97, 98, 100, 101, 103, 104,

105, 106, 108, 110, 112, 115, 116, 117

MA[22:0] 59, 61, 62, 64, 65, 66, 67, 68, 69, 70,

72, 73, 74, 75, 76, 78, 79, 80, 81, 83,

84, 85, 86

O

I/O Data for SDRAM, parallel Flash,

and ROM

Address for SDRAM and Flash.

Pins MA[10:8] strap into register

values as OCCLK_SEL[4:2], which

defines the CPU speed. For

RTL8671B/ RTL8671BH, the

[1]I

I

O

I

Word clock input from AFE

Master clock from AFE

Control data output to AFE

Dying Gasp voltage detect input

MA[10:8] should be strictly pulled

as ‘001’.

Integrated ADSL2+ Router Controller 6 Track ID: xxxx-nnnn-nn Rev. 0.4

[1]

SDCLK

MCS2#

107

88

O

O

RTL8671B/ RTL8671BH

Datasheet

SDRAM clock

Bank 0 chip select SDRAM chip

select.

MCS3# 90 O Bank 1 chip select SDRAM chip

select

OE#/RAS# 92 O Raw address strobe for SDRAM

interface; output enable for FLASH

interface

CAS#

WE#

91

94

O

O

Column address strobe

Write enable for SDRAM/ FLASH

interface

DQM[3:0] 66, 65, 68, 67 O DQM[3:0] for SDRAM; shared with

AA17, AA18, AA15, AA16

MCS0# 63 O ROM Bank 0 chip select for FLASH

memory

SFCS# 63 O Chip select of SPI FLASH interface

if enabled (AFPWDN pull-up on

power-on reset)

SFDI 35 I Serial data in of SPI FLASH

interface if enabled; shared with

AFCLWD

SFDO 62 O Serial data out of SPI FLASH

interface if enabled; shared with

MA20

SFCK 64 O Reference clock of SPI FLASH

interface if enabled; shared with

MA19

GPIO

GPIOA[7:5]

GPIOB[7:0]

43, 42, 25

52, 51, 50, 49, 48, 47, 46, 45

UART

UCTS# 43 I Clear to send; shared with GPA7

and SV_CK

URXD 45 I RX data; shared with GPB0 and

SV_CS#

UTXD 46 O TX data; shared with GPB1 and

SV_DI

Integrated ADSL2+ Router Controller 7 Track ID: xxxx-nnnn-nn Rev. 0.4

I/O

I/O

GPIO port A

GPIO port B

URTS#

47 O

RTL8671B/ RTL8671BH

Datasheet

Request to send; shared with

GPB2 and SV_DO

JTAG (shared with GPIOB7-3)

JTCK

JTMS

48

51

I

I

JTAG test clock; shared with GPB3

JTAG test mode select; shared with

GPB6

JTDO 52 O JTAG test data output; shared with

GPB7

JTDI 50 I JTAG test data in; shared with

GPB5

JTRST# 49

POWER & GND

I JTAG test reset; shared with GPB4

VDD12

VDD33

VSS

DGND

OVDD

IVDD

3, 9, 10, 13, 120

2, 14, 23, 125

6, 12, 17, 18, 123, 127

24, 58, 89, 111

39, 60, 71, 82, 93, 102, 113

26, 36, 44, 56, 77, 87, 99, 109

Misc

P

P

P

P

P

P

Analog 1.2V supply

Analog 3.3V supply

Analog ground

Digital ground

3.3V digital I/O supply

1.2V digital kernel supply

CK25MOUT 118 O Clock output of 25MHz for possible

peripheral use

VCTRL 1 O Output of the embedded regulator

controller to generate 1.2V VDD for

the kernel supply of the chip.

Connecting to an external PNP-BJT

base if used (BJT collector output

to IVDD); leaving no connection if

not used.

DTEST

TESTMODE

124

38

-

I

No used; leaving no connection

Test only; leaving no connection

Pulled-down internally for normal

operation

RSRVD(NC)

Notes

1.

15, 16, 53 - No used; leaving no connection

MA[10:9] and AFTXD[3:2] strap into the register at the power-on reset to configure the CPU speed. The value ‘00110’ configures the

CPU running at 340MHz. This is a strict setting for

RTL8671B/ RTL8671BH. That is, AFTXD3 and MA8 should be pulled up via a 4.7k

Ohm resistor, and AFTXD2 and MA[10:9] should be pulled low via a 4.7k Ohm resistor.

Integrated ADSL2+ Router Controller 8 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

Integrated ADSL2+ Router Controller 9 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

7. System Overview

TBD

Integrated ADSL2+ Router Controller 10 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

8. Electrical Requirements

8.1. DC Characteristics

8.1.1. Absolute Maximum Rating

Table 2

Parameters

I/O supply voltage

Core supply voltage

Storage temperature

ESD protection

Absolute Maximum Rating

Min

TBD

TBD

TBD

TBD

TBD

TBD

Max Unit

V

V

V

Symbol

VDDIO

VDDC

TSTG

VESD

8.1.2. Recommended Operation Conditions

Table 3

Parameters

Operating

temperature

Digital supply for I/O

ring

Core power supply

voltage

Input high voltage

Input low voltage

Input current

VIH

VIL

VIN

TBD

TBD

TBD

TBD

V

V

µA

VDDC TBD 1.2 TBD V

VDDR TBD 3.3 TBD V

Symbol

TA

Recommended Operation Conditions

Condition

Ambient

Min

TBD

Typ

TBD

Max

TBD

Unit

°C

8.1.3. Power Consumption

Table 4

Parametes

Digital supply for I/O ring

(3.3V)

* Power Consumption

Condition Estimated Power

TBD mA

Unit Symbol

VDDR ADSL (ADSL2+

interleaved mode),

and Ethernet are

active

Integrated ADSL2+ Router Controller 11 Track ID: xxxx-nnnn-nn Rev. 0.4

Core power supply voltage

(1.2V)

VDDC ADSL (ADSL2+

interleaved mode),

and Ethernet active

TBD

RTL8671B/ RTL8671BH

Datasheet

mA

Phy power supply voltage

(1.2V)

VDDPhy ADSL (ADSL2+

interleaved mode),

and Ethernet are

active

TBD mA

8.1.4. Reference Crystal

Table 5

Parameters

Center frequency

Shunt capacitance

Load capacitance

Crystal equivalent serial resistor

Aging

Frequency tolerance

Reference Crystal

Min

25

+/-50

Typ

Max Unit

MHz

pF

pF

Ω

ppm/yr

ppm

Symbol

fcf

Co

CL

CESR

8.1.5. ADSL Interface Clock Input

Table 6

Parameters

Clock frequency

Pulse duration high

ADSL Interface Clock Input

Symbol

fclock

tw(HI)

Min Typ

35.328

14.15

Max Unit

MHz

ns

8.2. AC Characteristics

8.2.1. FLASH – Parallel

Table 7

Symbol

TCS

Parameter

The timing interval between

F_CS0#(or F_CS1#) and WE#

Parallel FLASH Timing

Min. Typ. Max. Units

ns

Notes

Controlled by Reg.

0xB9000004(MTCR0)

Integrated ADSL2+ Router Controller 12 Track ID: xxxx-nnnn-nn Rev. 0.4

TWP

The timing interval for WE# to

pulled low (RAS# for read

operation).

RTL8671B/ RTL8671BH

Datasheet

Controlled by Reg. 0xB9000004

(MTCR0)

ns

A[20..0]F_CE0#OE#TwpTcsWR#D[n..0]

Figure 5 Flash Access Timing

8.2.2. FLASH – Serial

TBD

8.2.3. SDRAM

8.2.3.1

Symbol

TSETUP

SDRAM Input Timing

Table 8

Parameter

Input setup prior to rising edge

of clock. Inputs included in this

timing are D[31: 0] (during a

read operation)

SDRAM Input Timing

Min.

TBD

Typ.

Max.

Units

ns

Notes

THOLD

Input hold-time after the rising

edge of clock. Inputs include in

this timing are D[31: 0] (during

a read operation)

TBD TBD ns

Integrated ADSL2+ Router Controller 13 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

Figure 6 SDRAM Input Timing

8.2.3.2

Symbol

TCLK2OUT

SDRAM Output Timing

Table 9

Parameter

Rising edge of clock-to-signal

output. Outputs include this timing

are D[31: 0], CS0#, CS1#,RAS#,

CAS#, LDQM, UDQM, WE# (during

a write operation).

SDRAM Output Timing

Min.

TBD

Typ.

Max.

TBD

Units

ns

Notes

THOLDOUT

Signal output hold time after the

rising edge of the clock. Outputs

included in this timing are D[31: 0]

(during a write operation).

TBD TBD ns

Figure 7 SDRAM Output Timing

Integrated ADSL2+ Router Controller 14 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

8.2.3.3

Symbol

TREFRESH

TRCD

SDRAM Access Control Timing

Table 10 SDRAM Access Control Timing

Parameter

Auto-refresh timing

The time interval between

RAS# active and CAS#

active

TBD

Min. Typ. Max. Units

µs

ns

Notes

TRP The time interval between

pre-charge and the next

active

TBD ns

TRAS The time interval between

active and pre-charge

TBD ns

TRC The time interval between

active and the next active

TBD ns

TRFC The time interval between

auto-refresh and active

TBD ns

TCAS_LATENCY The data output delay after

The CAS# active

TBD ns

Figure 8 SDRAM Access Control Timing

Integrated ADSL2+ Router Controller 15 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

8.2.4. AFE

8.2.4.1

Symbol

F

Th

Master clock

Table 11 AFE Master Clock

Parameter

Clock frequency

Clock duty cycle

Min.

Typ.

35.328

50

Max.

Units

MHz

%

Notes

8.2.4.2

Symbol

Tvar

Transmission Interface

Table 12 AFE TX Interface

Parameter

Setup time before falling edge of clock.

Min.

12

Typ.

Max.

18

Units

ns

Notes

AFE

latch data

at falling

edge of

clock

8.2.4.3

Symbol

Ts

Reception Interface

Table 13 AFE RX Interface

Parameter

Data setup-time prior to falling edge of

clock

Min.

3

Typ.

Max.

Units

ns

Notes

Th Data hold-time after falling edge of clock 3 ns

8.2.5. JTAG

Table 14 JTAG Interface Timing

Symbol

TBSCL

TBSCH

TBSIS

Parameter

JTAG clock low time

JTAG clock high time

TDI, TMS setup time to rising edge of

TCK

Integrated ADSL2+ Router Controller 16 Track ID: xxxx-nnnn-nn Rev. 0.4

Min.

Typ.

Max.

Units

ns

ns

ns

Notes

TBSIH

TCK

TBSOH

TBSOD

TBSR

TBSRS

TDI, TMS hold time from rising edge of

RTL8671B/ RTL8671BH

Datasheet

ns

TDO hold time after falling edge of TCK

TDO output from falling edge of TCK

JTAG reset period

TMS setup time to rising edge of JTAG

reset

ns

ns

ns

ns

TBSRH TMS hold time from rising edge of JTAG

reset

ns

TCKTMS, TDITDO

Figure 9 Boundary-Scan General Timing

RESET#TMS

Figure 10 Boundary-Scan Reset Timing

Integrated ADSL2+ Router Controller 17 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

8.2.6. Reset

Table 15 Reset Timing

Symbol

TPOWERON_RESET

Parameter

Minimum time required to hold

the PWRRST# at logic 0 state

after stable power has been

applied to

RTL8671B/

RTL8671BH

Min.

Typ.

TBD

Max.

Units

µs

Notes

TPUSH_ESET

Minimum time required to hold

the PWRRST# at logic 0 state

for

RTL8671B/ RTL8671BH

system reset

TBD µs

3.3VTPOWERON_RESETTPUSH_RESETRESET#

Figure 11 Reset Timing

8.2.7. VREF Timing

Table 16 VREF Timing

Symbol

Tdelay

Parameter

Delay time from dying gasp

detect to ADSL dying gasp

indication bit clear

TRP

Required residual power sustain

time

Note1: 250*8*[(B+1)*M+R]*Tp*SEQ*D/(Lp*M)

Min.

Typ.

TBD

Max.

Units

us

Notes

1

ms

Integrated ADSL2+ Router Controller 18 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

8.2.8. Power-on sequence

TBD

Integrated ADSL2+ Router Controller 19 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

9. Mechanical Dimensions

Figure 12 Drawing of LQFP-128

Integrated ADSL2+ Router Controller 20 Track ID: xxxx-nnnn-nn Rev. 0.4

Table 17 Dimension of LQFP-128

RTL8671B/ RTL8671BH

Datasheet

Integrated ADSL2+ Router Controller 21 Track ID: xxxx-nnnn-nn Rev. 0.4

RTL8671B/ RTL8671BH

Datasheet

10. Ordering Information

TBD

Realtek Semiconductor Corp.

Headquarters

No. 2, Innovation Road II, Science-based

Industrial Park, Hsinchu, 300, Taiwan, R.O.C.

Tel: 886-3-5780211 Fax: 886-3-5776047

Integrated ADSL2+ Router Controller 22 Track ID: xxxx-nnnn-nn Rev. 0.4