Loop Compensation of Voltage-Mode Buck Converters

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Application Note ANP 16

Loop Compensation of Voltage-Mode Buck Converters

One major challenge in optimization of dc/dc power conversion solutions today is

feedback loop compensation. To the laymen of dc/dc power conversion circuits, this

concern can be not only difficult to understand, but a highly intimidating matter to

deal with. Various effects of feedback loop stability occur with application of

feedback compensation, which, if not properly calculated, can cause instability and

regulation failure to occur. This application note helps to clarify the more advanced

Type-III feedback loop compensation considerations in voltage-mode buck

converter applications, which are viewed as inherently more stable when compared

to current-mode conversion topologies.

Most designers believe the application of ceramic output capacitors is a good

design decision, for both their low cost, abundance of suppliers, and the inherently

low ESR. Ceramic capacitors are indeed a good choice for converter output

filtering, where relatively low capacitance is required. Ceramic capacitors offer low

Equivalent Series Resistance (ESR) that reduces output ripple. However, the

inherently low ESR of the typical ceramic output capacitor necessitates the use of a

Type-III compensation network. The Type-III compensation network, which is more

complicated than Type-II, will be explained in the following text.

Buck Converter System Block Diagram

The system block diagram of a Buck-Converter is shown in figure 1 where VIN

and

VOUt are converter input and output voltage respectively. The Error Amplifier and its

accompanying passive components comprise the compensation network

(compensation). The focus of this application note is the proper selection of these

passive components in order to meet compensation goals. Output of the

compensation network is the analog control signal Vc. The Pulse-width-Modulator

(Modulator) generates a duty-cycle D that is proportional to Vc. Duty-cycle control D

of power switches in conjunction with the filter produce the desired voltage VOUT

from VIN.

VIN

VREFERENCE

Compensated ErrorAmplifier

(Compensation)Vc

Pulse-Width

Modulator

(Modulator)

D

Power switches &LC output filter

(Power stage)

VOUT

Feedback Figure 1. System Block Diagram of Buck-Converter

Oct11-06 Loop Compensation of Voltage-Mode Buck Converters © 2006 Sipex Corp.

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Open-Loop Response

System response from the input of the Modulator to the output of the power stage is

called “Open-Loop Response”. It is shown in figure 2. The LC output filter gives rise

to a “Double-Pole” that has a -180 degrees phase shift. Double-Pole frequency fLC

is given by:

1fLC= ………………………….. (1)

2πLC

The ESR of output capacitor C gives rise to a “ZERO” that has a +90 degree phase

shift. ESR ZERO frequency fESR is given by:

1fESR= ……………………… (2)

2π.

Figure 2 shows two plots. The top plot is representative of the Open-Loop gain and

the lower plot shows the relevant phase. When the output capacitor is a small

ceramic type, fESR

can be significantly larger than fLC. In this case, the phase of the

open-loop reaches -180 degrees before the ESR Zero brings the phase to -90

degrees (see figure 2).

Gain (dB)20log(Vin/Vramp)-40dB/decf0 (dB)LCf >>fESRLC-20dB/dec0 (deg)-90 (deg)> -90deg/decPhase (deg)-180 (deg)+45deg/dec

Figure 2. Gain/Phase of the Open-Loop Response with ceramic output capacitor

Oct11-06 Loop Compensation of Voltage-Mode Buck Converters © 2006 Sipex Corp.

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Goals of Compensation

The goal of compensation is to design a feedback system such that the converter

will be stable and will quickly regulate the output against changes in input voltage or

load conditions. Quick response requires that the Loop 0dB cross-over frequency

“fc” (also known as bandwidth) be as high as practical. In general, compensation is

designed such that (fs/10)

converter. Stability criterion requires that the phase margin corresponding to “fc”

be greater than 45 degree where

Phase Margin = 180 degree + phase of Loop Gain

In essence we have to shape the Gain/Phase of the Error Amplifier such that when

combined with Gain/Phase of the Open-Loop of figure 2 it satisfies the above

requirements.

Type-III Compensation

Type-III compensation is realized by connecting resistors/capacitors to a controller’s

integral Error Amplifier as shown in figure 3. A nomenclature consistent with Sipex

datasheet is used. Transfer function of Type-III has two “Zeros” and two “Poles” at

the frequencies shown in figure 3. The combined effect of the Zeros results in a 180

degree phase boost. This phase boost is necessary to counter the 180 degree

phase lag due to the output filter double-Pole shown in figure 2 and generate the

required phase margin. In order to simplify the solution for the frequency of the 2nd

Zero and 1st Pole, components must be chosen so that CZ2>>CP1 and R1>>RZ3.

Further simplification can be made by making the frequency of the two Zeros

coincide. As stated above, the goal is to locate the Poles and Zeros of the

compensation such that the desired crossover frequency and corresponding phase

margin is obtained.

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CP1CZ3RZ3CZ2RZ2VoutR1-VcompVreference+

Conditions: CZ2>>CP1, R1>> RZ31/(6.28 RZ2 CZ2) 1/(6.28 RZ2 CP1)

1/(6.28 R1 CZ3)

1/(6.28 RZ3CZ3)

20log(RZ2/RZ3)Gain (dB)20log(RZ2/R1)frequency (Hz)+90Maximum boostpossible is 180 degreePhase (degree)frequency (Hz)-90

Figure 3. Type-III compensation and its associated gain/phase plots.

Six resistors and capacitors, when connected to the Error Amplifier as shown,

create a type-III compensation network. Component nomenclature is the same as

commonly used in Sipex datasheets. The frequency of the second “Zero” and first

“Pole” are simplified solutions based on choosing CZ2>>CP1, R1>>RZ3.

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Procedure for Calculating Type-III Components

As was mentioned, when a ceramic output capacitor is applied, the open loop

phase usually drops to -180 degrees or close to it. In order to achieve the required

phase margin of 45 degrees or greater (i.e., phase greater than -135 degrees), a

type-III compensation is needed to provide sufficient phase boost. Let’s assume

that the phase of open-loop system gain is the lowest possible, i.e., 180 degrees.

To get the minimum required closed-loop phase-margin of 45 degrees the

compensation must provide a +45 degree phase margin (i.e., a boost of 95

degrees). In order to maximize the boost, Poles and Zeros must be placed as far

apart as possible. We can now outline a step-by-step procedure for calculating

component values, as follows:

1.) Let R1=68.1kΩ. This value generally provides a satisfactory solution and helps

meet the requirement R1>>RZ3

2.) Place the second Zero at 60% of output filter’s double-Pole frequency and solve

for CZ3:

1CZ3=……………………………..… (3)

1zsf•R1•LCWhere

L and C are output inductance and capacitance respectively

zsf is Zero scale factor = 0.6

3.) To set fc to the desired value use the following equation and calculate RZ2 from:

(2•π•fc)•L•C+1VrampRZ2=x2•π•fc•CZ3Vin2…………….… (4)

Where

VRAMP is the ramp amplitude and VIN is converter’s input voltage

fc is typically set at 1/5 to 1/10 of switching frequency

fs

4.) Set the first Zero to coincide with the second Zero and calculate CZ2 from:

1CZ2=……………………………. (5)

1zsf•RZ2•LC5.) Set the first Pole at switching frequency of the converter

fs and solve for CP1:

1CP1=………………………………… (6)

2•π•RZ2•fs6.) Set the second Pole also at

fs and solve for RZ3:

1RZ3=…………………………………… (7)

2•π•CZ3•fs

Oct11-06 Loop Compensation of Voltage-Mode Buck Converters © 2006 Sipex Corp.

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Example 1.) Design compensation for a Buck converter with following specification:

VIN = 12V

Note: Loop Compensation component calculations discussed

VRAMP = 1.1V

in this application note can be quickly iterated with the Type III

fs = 900kHz

Loop Compensation Calculator on the web at:

L = 2.2uH

/files/Application-Notes/

C = 22uF

ESR = 3mΩ

fLC and fESR (calculated from 1 and 2 above) are 22.9kHz and 2.4MHz respectively.

Since fESR/fLC=105, clearly Type-III compensation has to be used.

Following the above procedure and letting fc=fs/9, we get:

R1 = 68.1kΩ

CZ3 = 170pF

RZ2 = 17.2kΩ

CZ2 = 673pF

CP1 = 10.2pF

RZ3 = 1.04kΩ

Figure 4 plots the actual SPICE simulation supporting these correct values for the

Type-III compensation network.

Figure 4. Spice simulation showing gain/phase for zsf=0.6, cross-over

frequency

fc is just over 100kHz and corresponding phase margin is 70

degrees

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Figure 5. Step load response corresponding to conservative compensation,

0A-2.5A, transient response is 75us

Practical Considerations (adjusting system response)

A key starting point of the above procedure is locating the Zeros at 60% of fLC

(i.e.,zsf=0.6). This, in general, provides a conservative solution. As seen in figure 4,

the phase margin of nearly 70 degrees is quite acceptable. However the tradeoff

between system response and system stability apply. As seen in figure 5, the

transient response is about 75us, not impressive for a 900kHz converter. For a

more aggressive compensation (i.e., faster transient response) locate the Zeros

closer to, or slightly above fLC (i.e., zsf > fLC). For instance if it is desired to get a

faster response for design example 1, let zsf=1.2. Recalculating components for

Example 1 we get:

R1 = 68.1kΩ

CZ3 = 85pF

RZ2 = 34.4kΩ

CZ2 = 168pF

CP1 = 5pF

RZ3 = 2.08kΩ

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Gain/phase for zsf=1.2 are shown in figure 4 and compared to the original solution.

As can be seen, mid-frequency gain is increased by 10dB and phase margin has

decreased 10 degrees with a minimum phase of about 30 degrees. Step load

response is shown in figure 6. As seen, the response time has been reduced

(improved) to a much faster 20us.

Figure 6. Step load response corresponding to aggressive compensation,

transient response has been reduced (improved) to 20us

Oct11-06 Loop Compensation of Voltage-Mode Buck Converters © 2006 Sipex Corp.

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Ramp amplitude (V)

1.1

1.0

1.1

1.0

1.1

1.0

1.1

Figure 7- Ramp amplitude of Sipex controllers

Part number

SP6132/H

SP6133

SP6134/H

SP6136

SP6137

SP6138

SP6139

Conclusion

With half a dozen simple, low-cost discrete components, and some creative

‘positioning’, Type-III compensation can greatly improve circuit response while

maintaining loop stability. The best part of this compensation case is the allowed

use of low cost ceramic output capacitors for the solution.

For further assistance:

Email:

WWW Support page:

Live Technical Chat:

Type III Loop Compensation

Calculator:

Sipexsupport@

/?p=support

/sipex/

/files/Application-Notes/

Oct11-06 Loop Compensation of Voltage-Mode Buck Converters © 2006 Sipex Corp.

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